Integrated circuits find wide-ranging use for applications such as microprocessors, microcontrollers, and application-specific integrated circuits. One category of integrated circuits include metal oxide semiconductor (MOS) transistors. MOS transistors generally include a gate electrode formed over the semiconductor wafer, with the gate electrode being insulated from the semiconductor wafer by a thin layer of gate insulator material. A source and a drain are spaced apart regions of either N-type or P-type semiconductor material and are generally embedded within the semiconductor wafer adjacent to the gate electrode on either side thereof. A region in the semiconductor wafer between the source and the drain, and beneath the gate electrode, forms a channel of the MOS transistor.
Traditionally, the gate electrode is formed from a semiconductor material such as polysilicon. However, due to polysilicon depletion and threshold voltage shifts attributable to boron penetration into the channel region that severely degrade device performance, the semiconductor industry began investigating metal gate electrodes as a replacement for polysilicon gate electrodes. Replacement of polysilicon with a metal gate electrode solves both the boron penetration and the polysilicon depletion issues.
One challenge to the replacement of polysilicon gate electrodes with metal gate electrodes is process integration into conventional transistor processing. Many candidate metals for the metal gate electrodes will not sustain high temperatures associated with a standard source/drain activation anneal due to either unwanted reactions involving the metals at the high temperatures or due to low melting temperatures of many candidate metals.
One proposed technique for forming metal gate electrodes includes forming a sacrificial mandrel followed by subsequent removal of the sacrificial mandrel and metal filling to form the metal gate electrodes, also known in the art as replacement metal gate (RMG) fabrication. In RMG fabrication, the sacrificial mandrel is formed over a sacrificial dielectric layer on a semiconductor substrate over the sacrificial dielectric layer, followed by optional ion implantation into source/drain regions in the semiconductor substrate. Sidewall spacers are then formed adjacent sidewalls of the sacrificial mandrels. The sidewall spacers are formed by an anisotropic etch of a blanket-coated, generally dielectric, layer overlying the mandrel. Because sidewall spacers are formed by an anisotropic etch along the sidewall of a substantially straight-walled sacrificial mandrel, the sidewall spacers typically have a lower portion that is proximal to the base substrate and that has a substantially perpendicular outer surface relative to the base substrate and an upper portion that is spaced from the base substrate and that has a sloped outer surface. Following formation of the sidewall spacers, a dielectric layer is formed over the base substrate with the dielectric layer abutting at least a portion of the sloped outer surface of the sidewall spacers. The upper portion of the sidewall spacers, along with an adjacent portion of the sacrificial mandrels, is selectively removed, thereby leaving the lower portion of the sidewall spacers in place. The remaining portions of the sacrificial mandrel are selectively etched, leaving the lower portion of the sidewall spacers in place. The lower portion of the sidewall spacers are employed as an etch mask to etch through the sacrificial dielectric layer, followed by filling the recess with a gate insulator to form a gate dielectric layer and metal to form the replacement metal gate electrode. The main advantage of using the RMG technique outlined above is that it avoids thermal and plasma damage to the gate dielectric layer and the metal gate electrode that may otherwise occur if the metal gate electrode is present earlier in device fabrication.
One problem with the aforementioned RMG techniques, or any fabrication technique that involves recess formation in the manner described above followed by filling of the recess, is that removal of the upper portion of the sidewall spacers and adjacent sacrificial mandrel results in a re-entrant profile of the resulting recess that is defined in the gate dielectric layer. Due to the re-entrant profile of the recess, filling the recess with electrically-conductive material is challenging and often results in unsatisfactory filling of the recess.
Accordingly, it is desirable to provide methods of forming integrated circuits in which recesses are formed in a dielectric layer using a sacrificial mandrel and sidewall spacers adjacent to sidewalls thereof while alleviating the re-entrant profile of the recesses. Further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.